Figure 2 from A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells | Semantic Scholar
High speed and low power preset-able modified TSPC D flip-flop design and performance comparison - YouTube
TSPC Logic - YouTube
digital logic - True single phase clock based flip flop - Electrical Engineering Stack Exchange
Figure 2 from A NOVEL DESIGN OF COUNTER USING TSPC D FLIP-FLOP FOR HIGH PERFORMANCE AND LOW POWER VLSI DESIGN APPLICATIONS USING 45 NM CMOS TECHNOLOGY Ms . | Semantic Scholar
help on a design on a high speed TSPC flip flop design. : r/AskElectronics
TSPC D-flip-flop with SET and RESET lines. | Download Scientific Diagram
International Journal of Soft Computing and Engineering
Configuration of TSPC D flip-flops (D-FF) for the asynchronous circuit.... | Download Scientific Diagram
PDF] High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop | Semantic Scholar
Low Power based Dynamic TSPC D flip flop for High Performance Application based on GNRFET
how to choose device sizing for a TSPC edge triggered DFF? | Forum for Electronics
A TSPC DFF sizing & simulation | Forum for Electronics